Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!HERMES.BERKELEY.EDU!dillon
From: dillon@HERMES.BERKELEY.EDU (Matt Dillon)
Newsgroups: comp.sys.amiga
Subject: Re: GVP 68030 reviewed in Sentry / 68040
Message-ID: <8906122351.AA02603@hermes.Berkeley.EDU>
Date: 12 Jun 89 23:51:13 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Lines: 27

:Well, yes and no.  The caches on both '030 and '020 are straight mapped 256
							 ^
:byte caches.  They're organized a bit differently, the '030 caches are both

	direct mapped.

				:-)

:Note that this is all very '020/'030 specific; the '040, or either '020/'030
:with external cache, will no doubt behave very differently.  You'll likely
:have more obvious cache support in the OS by then, though...

	From the rumors I've heard, the 040 will have two 4K caches,
one for data and one for code, each is 4-way associative so it won't work.
The 68040 will have a harvard architecture internally.  Motorola commented
that it had learned a lot from the 88000 series and many 040 instructions
will achieve single cycle execution.

	Intel's 80486 will have a single 8K 4-way associative cache (same
total amount).  I seem to remember them saying that the chip internal busses
will be 128 wide but can't be sure.  As far as I can tell, they are moving
towards maximum functional integration and just throwing more bits at their
busses to achieve the throughput... sort of like their silly little Risk
chip that began as a coprocessor.


				-Matt