Path: utzoo!utgpu!watmath!isishq!f171.n221.z1.FIDONET.ORG!David.Johnson
From: David.Johnson@f171.n221.z1.FIDONET.ORG (David Johnson)
Newsgroups: comp.sys.cbm
Subject: Re: REU Hacking.
Message-ID: <2482.2487586D@isishq.FIDONET.ORG>
Date: 2 Jun 89 07:01:26 GMT
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Organization: FidoNet node 1:221/171 - Izot's Swamp, Kitchener ON
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 > ]at your own risk....
 > ]
 >
 > Gee, my supply runs three 64's with no problems.... not
 > to mention a
 > host of other hardware.  (Turn *THAT* into a pile of ash
 >  :-)
 >
 
If and when it does fail (and you are courting disaster) learn from 
someone with experience you may lose some ram chips and possibly a 
rom/pal chip!  (I've lost 2 ram chips and my Fload cart due to a flaky 
power supply)
 
 > lines revealed that the only "special" lines the REU appears
 > to use
 > are BA (Bus Available), DMA (Direct Memory Access), and
 > the I/O line
...
> I decided to play with DMA,...
 > Shack is closed at 2am), and everything seemed to work
 > fine.
 >
 > But it doesn't.  If you try anything "complex," it mangles
 
From the information provided in the 128 prog ref manual re: DMA access 
you have to be very carefull of the state of the phase clock and access 
the dma when the vic chip is not accessing the dma chip.  There was 
other items re: that the dma will occur after 2 clock cycles after 
access. "All DMA sources must yield to the vic diring phase 0 or ba 
low.  Maybe your problem is with phase 0 as you apparently have dealt 
with ba
 
From what I've gathered by looking at the MMU map and various system 
maps I'm lead to believe that the C128 can access either 256/or 512 
K internally.  (references to bank 2/3 ram) (pla pin 27 128/256?) any 
ideas?
 
Any information on the 6551 uart as was designed for use with cp/m 
would also be appreciated.  Perhaps this is the standard that should 
be adopted and maybe if enough of us authors support it it may be commercially 
viable 



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