Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!zaphod.mps.ohio-state.edu!swrinde!ucsd!ucsdhub!hp-sdd!hplabs!hpda!hpwala!hpavla!gary
From: gary@hpavla.HP.COM (Gary Jackoway)
Newsgroups: comp.ai
Subject: Re: simmulated annealing
Message-ID: <1830002@hpavla.HP.COM>
Date: 14 Dec 89 17:24:27 GMT
References: <558@granite3.UUCP>
Organization: Hewlett-Packard Avondale Division
Lines: 21

Simulated Annealing has been used in the field of IC and Printed
Circuit design, specifically in the placement of parts on the
chip or board.  If you get a copy of any of the last 3 DAC's
(design automation conference proceedings), you'll see plenty
of articles on the subject.  Paper 35.1 from the 1986 conference
gives an overview of papers before that date.

I attended several of the discussions concerning the worthiness
of SA in the autoplacement field and the bottom line was this:
SA with correct temperature control gives excellent results,
perhaps better than current methods can manage;  you have to
be willing to wait (and wait, and wait...).  SA is very slow.
The major issue was whether the time it takes was worth it.
(If its ten times slower than an existing method, then you
can use that existing methods ten times with different starting
positions and different placement modification rules, and keep
the best result.)

Hope this helps.

Gary Jackoway