Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!dg!chris
From: chris@dg.dg.com (Chris Moriondo)
Newsgroups: comp.arch
Subject: R6000 FPU question
Message-ID: <241@dg.dg.com>
Date: 13 Dec 89 21:05:04 GMT
Reply-To: uunet!dg!chris (Chris Moriondo)
Distribution: na
Organization: Data General, Westboro, MA.
Lines: 14

Can anyone who is familiar with the MIPS R6000 tell me, is the
floating-point adder function unit pipelined?  I am assuming that ADD
can proceed in parallel with MUL (DIV,SQRT), but can more than one
ADD be executing in parallel?  (Note, I know that the instruction
fetch, decode, etc. is pipelined, that is not what I am asking.)
Since they are using the BIT multiplier chip I assume that only one
MUL/DIV/SQRT can execute at a time.

Anyone care to speculate as to how much pipelining add would win/lose
in terms of useful overlap in FP codes versus increased latency? 

thanks,

-chrism