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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Pipelined FP add
Message-ID: <33570@hal.mips.COM>
Date: 14 Dec 89 17:35:01 GMT
References: <241@dg.dg.com>
Reply-To: mark@mips.COM (Mark G. Johnson)
Distribution: na
Organization: MIPS Computer Systems, Inc.
Lines: 25

In article <241@dg.dg.com> uunet!dg!chris (Chris Moriondo) writes:
  >
  >Anyone care to speculate as to how much pipelining add would win/lose
  >in terms of useful overlap in FP codes versus increased latency? 
  >

Several articles were posted to comp.arch this spring, talking about the
perceived benefits of a pipelined FP adder in the Motorola MC88K risc.
Perhaps the Moto folks can say more now.  [ after the departure of Ross ]

I dimly recall that the last time around, they were beginning to feel
that the 88K's shared register file -- same regs for integer and FP
operands -- required large numbers of read and write ports to make
FP programs run quickly.  The other design alternative, separate
integer regs from the FP regs, has lots of ports already since it's
2 copies of the hardware.  I'm sure if my memory is faulty somebody
will gently correct me.

The eariler MC88K articles were posted by wca@oakhill.UUCP and
mpaton@oakhill.UUCP; your site archives may contain comp.arch article
<1362@oakhill.UUCP>.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}