Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uwm.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!uxa.cso.uiuc.edu!afgg6490
From: afgg6490@uxa.cso.uiuc.edu
Newsgroups: comp.arch
Subject: Re: VME Bus Standard
Message-ID: <112400018@uxa.cso.uiuc.edu>
Date: 15 Dec 89 10:32:31 GMT
References: <11759@phoenix.Princeton.EDU>
Lines: 18
Nf-ID: #R:phoenix.Princeton.EDU:11759:uxa.cso.uiuc.edu:112400018:000:709
Nf-From: uxa.cso.uiuc.edu!afgg6490    Dec 14 20:09:00 1989


Another RISC bus suggestion:

-> Don't have combined A/D lines.

Although it is very attractive to take your 32 address lines
and your 32 data lines and combine them for a 64 bit wide data path,
it is a lot sillier when you have 256 lines in total (an extra 32
address lines gets lost in the shuffle).

There are a lot of address only data transactions, in a cache coherent system.

Conversely, the block data transfers that we are trying to optimize
with 256 bit transfers would tend to use the data bus for a long time.
(Is this true? I/O transfers use blocks >> 256 bits, but do (should) cache 
systems...)
So address only transactions for processors get blocked by block transfers
for I/O.  Let em pass.