Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!rutgers!rochester!rit!cci632!walden!jjg
From: jjg@walden.UUCP (John Grana)
Newsgroups: comp.arch
Subject: Re: VME Bus Standard
Keywords: VMEbus, 64 bit cycles
Message-ID: <136@walden.UUCP>
Date: 16 Dec 89 21:24:51 GMT
References: <11759@phoenix.Princeton.EDU> <112400018@uxa.cso.uiuc.edu>
Reply-To: jjg@walden.UUCP (John Grana)
Organization: Awcs Inc.   Henrietta, New York
Lines: 30

In article <112400018@uxa.cso.uiuc.edu> afgg6490@uxa.cso.uiuc.edu writes:
>
>Another RISC bus suggestion:
>
>
>Although it is very attractive to take your 32 address lines
>and your 32 data lines and combine them for a 64 bit wide data path,
>it is a lot sillier when you have 256 lines in total (an extra 32
>address lines gets lost in the shuffle).
>
Speaking of combining the address and data lines for a 64 bit data
path, the latest VMEbus specification (rev. D?) will define a new
type of block transfer mode - BLT64 or VME64 (I'm not sure what they
plan on calling it). It is like the present Block Mode (address/data
cycle then data only) except that:

	1) The first cycle is an address only cycle.
	2) All cycles after that are 64 bits (both the address and
	   data lines transfer the data).
	3) 1 or 2 new timing parameters have been added (I don't recall
	   what they are...)

John Peters from Performance Technologies Inc in Rochester NY came up with
the initial timing and byte lane ordering. He also designed a "proof of
concept" board set and is running > 60 Mbytes/sec on various VMEbus
backplanes.


John Grana
jjg@walden.UUCP