Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!wuarchive!decwrl!shelby!neon!carcoar.Stanford.EDU!wilson From: wilson@carcoar.Stanford.EDU (Paul Wilson) Newsgroups: comp.arch Subject: Japanese Josephson breakthrough? Implications? Message-ID: <1989Dec18.025843.4435@Neon.Stanford.EDU> Date: 18 Dec 89 02:58:43 GMT Sender: USENET News System Reply-To: wilson@carcoar.Stanford.EDU (Paul Wilson) Organization: U. of Illinois at Chicago (UIC, *not* UofC or UIUC) Lines: 45 One of the newsbytes groups (clari.nb.trends) has an article that says the Japanese are claiming to have built a working Josephson computer. They say it's got 26,000 Josephson devices (in 4 chips) on a 10*10 cm board cooled to -268.8 degrees Celsius, and it executes a BILLION (note the B) instructions a second. Consuming 6.2 milliwatts. I'd guess that's for a small in-Josephson-memory program! Hmmm... So I wonder, are we going to switch to bytecoded stack machine uniprocessors? (Or nybblecoded, even?) Locality of reference could be the most important research topic of the next decade. The speed difference between RAM and these CPUs could be like the difference between disks and RAMs. How about centralized cold computer rooms with timeshared barrel processors fed by gigabyte RAIDS (redundant arrays of inexpensive DRAMS :-). Then again, maybe it's cold fusion all over again... even so, it's fun to consider the implications. The return of reference counting? The death of shared memory? Lots of fine-grained optimistic computing to avoid waiting for memory? Any comments on this alleged Japanese breakthrough? Is it true? If so, what does it really mean? Paul R. Wilson Software Systems Laboratory lab ph.: (312) 996-9216 U. of Illin. at C. EECS Dept. (M/C 154) wilson@bert.eecs.uic.edu Box 4348 Chicago,IL 60680 Paul R. Wilson Software Systems Laboratory lab ph.: (312) 996-9216 U. of Illin. at C. EECS Dept. (M/C 154) wilson@carcoar.stanford.edu Box 4348 Chicago,IL 60680