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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Re: Japanese Josephson breakthrough?  Implications?
Message-ID: <33818@mips.mips.COM>
Date: 18 Dec 89 14:47:05 GMT
References: <1989Dec18.025843.4435@Neon.Stanford.EDU>
Sender: news@mips.COM
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Sunnyvale, CA
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In article <1989Dec18.025843.4435@Neon.Stanford.EDU> wilson@carcoar.Stanford.EDU (Paul Wilson) writes:
  >One of the newsbytes groups (clari.nb.trends) has an article
  >that says the Japanese are claiming to have built a working
  >Josephson computer. 
  >
  >They say it's got 26,000 Josephson devices (in 4 chips)
  >on a 10*10 cm board cooled to -268.8 degrees Celsius,
  >and it executes a BILLION (note the B) instructions
  >a second.  Consuming 6.2 milliwatts.
  >
  >I'd guess that's for a small in-Josephson-memory program!


If true this is a big step forward in digital JJ's; the previous "record"
was a chip that contained 8,454 Josephson interferometers (2,066 gates):

    Y. Hatano et al, "A 4-bit Josephson Data Processor Chip", IEEE Journal
    of Solid-State Circuits, Vol. 24 No.5 (Oct 1989) pp. 1312-1316.

Note that the researchers chose to build a 4-bit machine.  Perhaps the
4 chip, 20K-JJ (~~5K gate?) "computer" mentioned above is indeed a 4-bit
CPU plus 512 byte SRAM???

One or two properties of digital JJ circuitry may be of interest here:

    1.  Every signal wire is a (superconductng) transmission line of rather
        low impedance, below 5 ohms.  So every signal has enough "oomph"
        to drive off-chip; there is no fan-up penalty for pad drivers.

    2.  Signals are low-amplitude voltages, on the order of 2.5 millivolts.
        (See Figures 5, 8 & 10 of the Hatano paper.)  They have to be;
        otherwise driving the low-Z transmission lines would consume
        excessive power.   It is left as an exercise to the reader to
        interface an F100K ECL SRAM chip (that wants 700mV inputs) with
        2.5mV signals from a CPU.

    3.  Power to the JJ interferometers is supplied via the clocks; there
        is no DC supply.  In Hatano's 4-bit processor, these were 1.02 GHz
        100 mV sine waves (and they had to supply 25mW of power).  It
        might be difficult to implement truly asynchronous logic in this
        family.

    4.  OR gates, AND gates, and flip-flops were attained by Hatano.
        Interestingly he doesn't mention inverting gates.  OR gates took
        9.0 picoseconds, AND gates took 19.4 picoseconds.


I don't mean to rain on the JJ parade; merely to suggest that the "computer"
alluded to above may not be a 32-bit machine with floating point,
virtual memory, and MS-DOS compatibility.   :-)
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}