Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!philmtl!atha!rwa
From: rwa@cs.AthabascaU.CA (Ross Alexander)
Newsgroups: comp.arch
Subject: _really_ ciscy (was: Re: VME Bus Standard)
Keywords: Futurebus, RISC
Message-ID: <1328@atha.AthabascaU.CA>
Date: 18 Dec 89 20:26:42 GMT
References: <7172@pt.cs.cmu.edu> <112400007@uxa.cso.uiuc.edu> <390@blenheim.nsc.com> <411@blenheim.nsc.com>
Organization: Athabasca University
Lines: 20

des@dtg.nsc.com (Desmond Young) writes:
>  This does hint at the very (very) CISC nature of Futurebus+. It has
>every facility (almost) ever dreamt of. As an analogy to CISC
>processors, it almost has a single instruction to compile a program :-).

   Now hold on a minute, didn't the Fairchild SYMBOL machine have a
single instruction that would do a compile (in a random hardware
implementation, as I remember).  It was a pretty ugly language
grammatically but the compilations just blazed through.

> (Well, a wee bit of an exaggeration).

   Hell no.  I'm serious.

>Anyway, if you want to go fast, it has too much baggage.
>My Opinion etc.

   Agreed.
--
rwa@aungbad.AthabascaU.CA	Ross Alexander (403) 675 6311