Path: utzoo!attcan!uunet!samsung!zaphod.mps.ohio-state.edu!mips!hal!mark From: mark@mips.COM (Mark G. Johnson) Newsgroups: comp.arch Subject: Re: Futurebus+ @ 500MBytes/sec Message-ID: <33845@mips.mips.COM> Date: 19 Dec 89 15:31:53 GMT References: <276@leia.WV.TEK.COM> Sender: news@mips.COM Reply-To: mark@mips.COM (Mark G. Johnson) Organization: MIPS Computer Systems, Inc. Lines: 38 In article <276@leia.WV.TEK.COM> johnt@opus.WV.TEK.COM (John Theus) writes: > >As I stated in a previous posting, we expect to be building Futurebus+ >hardware in the coming year that can sustain 500 Mbytes/sec on a 64 bit >wide data path. The questions that immediately come to mind are either >this does meet your definition for "fast", or you don't believe we can >deliver this bandwidth. Could you explain what is meant by "sustain" above? At least two really cool things might be implied by this: (1) In the coming year you'll be building Futurebus+ hardware that can transfer 512 bytes (i.e. 128 words, or 64 bus-widths of data) in 1024 nanoseconds. This'd be a cache refill from main memory. (2) In the coming year you'll be building Futurebus+ hardware that can do a DMA transfer of 50 Megabytes in 0.1 second. Are either of the assertions above correct? {they're based on the assumption that (500 MB/sec / 8 bytes/transfer) = 62.5 Mtransfers/sec = 16ns/transfer is the bus cycle time in "sustained" operation} Also, folks might think it was a bit smelly to claim high throughput rates for a "bus" that only has two or three slots, or for a "bus" that doesn't involve a printed circuit backplane board having connectors or sockets for separate daughterboards. Just to lay these types of silly "oh-yeah?" questions to rest permanently, Does next-years-500MB/sec-Futurebus+ have a mother/daughterboard construction with N>6 connectors and card slots, and will it run at 500 MBytes/sec when fully populated? Thanks. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}