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From: stevew@wyse.wyse.com (Steve Wilson xttemp dept303)
Newsgroups: comp.arch
Subject: Re: _really_ ciscy (was: Re: VME Bus Standard)
Keywords: Futurebus, RISC
Message-ID: <2561@wyse.wyse.com>
Date: 19 Dec 89 16:54:04 GMT
References: <7172@pt.cs.cmu.edu> <112400007@uxa.cso.uiuc.edu> <390@blenheim.nsc.com> <411@blenheim.nsc.com> <1328@atha.AthabascaU.CA>
Sender: news@wyse.wyse.com
Reply-To: stevew@wyse.UUCP (Steve Wilson xttemp dept303)
Organization: Wyse Technology
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In article <1328@atha.AthabascaU.CA> rwa@cs.AthabascaU.CA (Ross Alexander) writes:
>des@dtg.nsc.com (Desmond Young) writes:
>>  This does hint at the very (very) CISC nature of Futurebus+. It has
>>every facility (almost) ever dreamt of. As an analogy to CISC
>>processors, it almost has a single instruction to compile a program :-).
>
>   Now hold on a minute, didn't the Fairchild SYMBOL machine have a
>single instruction that would do a compile (in a random hardware
>implementation, as I remember).  It was a pretty ugly language
>grammatically but the compilations just blazed through.

This is a non-sequitor to the entire thread!  Des was trying to 
come up with an analogy between CISC and a bus standard.  The
fact that the SYMBOL box might have had an instruction to do 
this has  no real connection. 

Along this line maybe its time for some new acronyms to describe 
a Complicated Standard Bus (CSB?) or a Simple Standard Bus (SSB -
no wait - that stands for Single Side Band...) I know, how about
Easy Standard Bus (ESB).

Anyone have any better suggestions?

Steve Wilson