Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!mcsun!ukc!kl-cs!nott-cs!ucl-cs!M.Nigri
From: M.Nigri@ucl-cs.UUCP
Newsgroups: comp.lsi.cad
Subject: Re: description language MODEL
Message-ID: <485@ucl-cs.UUCP>
Date: 21 Dec 89 15:07:37 GMT
Sender: M.Nigri@ucl-cs.UUCP
Lines: 35

From: "Meyer E. Nigri" <M.Nigri@uk.ac.ucl.cs>

Dear Paul,

        I am a Research Student at University College London
working with Silicon Compilation with a special interest in
Neural Networks. I am currently considering the usage of VHDL
as an intermediate step between the neural network
specification language and its hardware implementation
(probably using SOLO 2XXX).

        I read your message in a bulletin board.  I know
nothing about MODEL, but here in UCL we are using SOLO 2XXX,
which uses EDIF as the input language. (What is the connection
between MODEL and EDIF ?)

        Do you know if there is any software tool that inputs
VHDL, rather than EDIF or MODEL, into SOLO. Or any software
that maps VHDL into EDIF or MODEL ?

        I look forward to exchange ideas with you.

        Yours sincerely,

        Meyer.

+--------------------------+-----------------------------------------------+
|Meyer Elias Nigri         |   JANET:mnigri@uk.ac.ucl.cs                   |
|Dept. of Computer Science |  BITNET:mnigri%uk.ac.ucl.cs@UKACRL            |
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