Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!swrinde!ucsd!ucbvax!pro-generic.cts.com!ericmcg
From: ericmcg@pro-generic.cts.com (Eric Mcgillicuddy)
Newsgroups: comp.sys.apple
Subject: Re: Speedy WDC Chips (was Re: Apple II
Message-ID: <8628.infoapple.net@pro-generic>
Date: 14 Dec 89 18:46:32 GMT
Sender: usenet@ucbvax.BERKELEY.EDU
Organization: The Internet
Lines: 9

In-Reply-To: message from rnf@shumv1.uucp

I disagree with your calculations. The fastest a double byte can be written to
memory is three cycles. Since the 65xxx series uses a fetch execute sequence,
1 cycle is used to get the instruction, another cycle is used to get the first
byte (8 bit data paths right?) and a third to get the second data byte. Since
the address lines and data lines are multiplexed, the addres must be latched
somewhere to clear the path for data. This may be what is slowing down the
works. I'll have to take a close look once I get one infront of me.