Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!rutgers!uwm.edu!bionet!ames!dftsrv!mimsy!chris
From: chris@mimsy.umd.edu (Chris Torek)
Newsgroups: comp.arch
Subject: Re: MIPS R[23]000 and Kane's book
Message-ID: <21414@mimsy.umd.edu>
Date: 22 Dec 89 19:49:13 GMT
References: <10279@alice.UUCP>
Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742
Lines: 64

In article <10279@alice.UUCP> jmk@alice.UUCP (Jim McKie) writes:
>Also, the instruction opcode bit encoding tables
>are possibly the most obscure way the information could be
>presented.

(hi jim)

(p. A-87)  The `opcode' and `special' tables are fine; it is
only the `bcond' and the two `cop' tables that are bogus.

>However, to be fair, it does mention that placing a branch
>instruction in a branch-delay slot is undefined (page A-7),
>and 'noreorder' is (indirectly) defined on pages C-5 and C-6.

There is more on reorder/noreorder under `.set' on p. D-16.  None of
the above can be found in the index (I looked before posting).  The
only excuse I have for missing them the first time is brain fatigue (I
read the book all at once).

After some email conversation, I have found out how to describe
returning from exceptions:

	To return from an exception, load the return address into
	one of the two reserved kernel registers (k0 or k1) and do
	a `j k0; rfe' (or j k1; rfe).  Typically EPC is the return
	address, but see below.  In this description, `EPC' refers
	to the numeric value in EPC, and `return' means to return to
	the address given by this value.

	If the `BD' bit is not set:

		The instruction that trapped (and thus did not
		complete, and did not modify the machine state) is at
		EPC.

		If the instruction is to be retried, return.  If the
		instruction is to be skipped, add 4 to EPC and return.
		If the instruction is to be simulated, simulate it, add
		4 to EPC (to skip it), and return.

	If the `BD' bit is set:

		The instruction that trapped is at EPC+4.

		If the instruction is to be retried, return.  (This
		re-executes the branch, but this is safe since branches
		modify no machine state save the PC, which will be
		overwritten as part of the return sequence.)  If the
		instruction is to be skipped or simulated, the branch
		instruction at EPC must be simulated first (using
		machine state as of the trap) to compute the return
		address.  Once this is done, the trapped instruction
		may be simulated or simply ignored.  Once this is done,
		return to the address calculated by the first
		simulation.

I believe this description is correct.

Now all you need is a list of which instructions are to be retried,
which are to be simulated, and which are to be skipped.  This depends
on the source of the interrupt too.
-- 
In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163)
Domain:	chris@cs.umd.edu	Path:	uunet!mimsy!chris