Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch
Subject: Cellular Automata Processors
Message-ID: <25405@cup.portal.com>
Date: 27 Dec 89 05:03:41 GMT
Organization: The Portal System (TM)
Lines: 28

The current issue of Scientific American has an article on cellular
automata which started me thinking about hardware implementations
of cellular automata engines.  It turns out that this problem maps really
well into hardware;  DRAM can store cell states and SRAM can be used for
look-up tables and line buffers.  My quick sketch of a low-cost 8 MHz
engine would run the life game at 128 Mcells/sec.  Wireworld would run at
8 Mcell/sec.  These cell counts do not include "dead" or "background"
cells, or cells in neighborhoods which haven't changed recently, due to
use of a sparse encoding.

The wireworld simulation is fast enough to implement a small 6502-like
processor, some RAM and some ROM, and still run well over 1000 generations
per second.

That would be fun because it could take input from a keyboard and generate
text.

I discussed this circuit with a friend of mine, and he said he remembers 
someone was selling hardware cellular automata engines for the IBM PC a
few years ago.

Does anybody know the details about that, or any other, dedicated processor
for cellular automata?  For example, how many did they sell?  How fast was
it?  Did it use a sparse encoding, or was there a memory representation
for every cell?  What limits did it have in terms of array size and
number of active cells?  What numbers of bits-per-cell did it support?
What did it cost?  How many chips did it have?  What sort of interfaces
were supported?