Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!cs.utexas.edu!rutgers!att!cbnewsh!beyer
From: beyer@cbnewsh.ATT.COM (jean-david.beyer)
Newsgroups: comp.arch
Subject: Re: Integer Multiply/Divide on Sparc
Summary: If you are willing to spend the money, complexity, chip area...
Message-ID: <6928@cbnewsh.ATT.COM>
Date: 29 Dec 89 14:04:18 GMT
References: <84768@linus.UUCP> <8840004@hpfcso.HP.COM> <84983@linus.UUCP> <34000@mips.mips.COM>
Organization: AT&T Bell Laboratories
Lines: 18


As I recall, the Naval Ordonance Research Computer (NORC) had a completely
combinatorial multiplier: it could do a 10 digit by 10 digit multiply in
the same number of cycles as an add. My recollection is that the multiplier
box took a refrigerator size box. The rest of the cpu  took another refrigerator
size box. And that  was in vacuum tube days.

So multiply instructions need take no longer than the total number of
gate delays to make such a thing. The main design question remains:
for the kind of work to be done with the processor, is that the best place
to put the complexity and delays and chip area. One must know the work to
be done; i.e, the benchmarks to be run (and whether they  are really
representative of the work to be run).
-- 
Jean-David Beyer
AT&T Bell Laboratories
Holmdel, New Jersey, 07733
attunix!beyer