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From: ed@iitmax.IIT.EDU (Ed Federmeyer)
Newsgroups: comp.arch
Subject: Context switching on RISC chips
Message-ID: <3167@iitmax.IIT.EDU>
Date: 30 Dec 89 21:07:08 GMT
Reply-To: ed@iitmax.iit.edu (Ed Federmeyer)
Organization: Illinois Institute of Technology
Lines: 28

One of the things that seems to characterize RISC chips is the relatively
large number of registers.  This makes me wonder what happens during a
context switch.  After all, moving 256 (or more) registers to memory, and
then another 256 (or more!) back in for each context switch seems like an
awfull lot of overhead.  I can think of a few ways around this:

1) Do nothing special... Suffer
2) Have each register "tagged" like a cache, so only the "dirty" registers
   need to be moved out.  You'd still have to load in all the old ones.
3) Have a few register "sets".  Ie, a context switch really moves a pointer
   to a bank of registers (of which there are several on-chip).
4) Like 3, but only have 2 sets.  While context 2 is processing, drain out
   context 1's set so it's ready by the next switch.  Since a RISC chip
   seems to execute 1 instruction in 1 cycle, I can't see that there is
   alot of extra bus cycles. (Unlike in a CISC, where you might have hundreds
   of clock cycles free while the processor executes an instruction in which
   the bus is not being used)  Unless of course you have a second bus
   going to memory dedicated to just shuttling registers in and out.

Are any of these sorts of techniqes being used in real RISC chips?  Or
am I just over estimating the overhead of RISC context switching?  If I get
some Email responses to this, I'll post a summary.
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