Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: Integer Multiply/Divide on Sparc
Message-ID: <4258@scolex.sco.COM>
Date: 30 Dec 89 20:32:08 GMT
References: <84768@linus.UUCP> <15418@vlsisj.VLSI.COM> <85138@linus.UUCP>
Reply-To: seanf@sco.COM (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 22

In article <85138@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes:
>:There should be instructions on the order of "multiply step" and "divide 
>:step", each of which will do one of the 32 adds/subtracts and then shift.  
> 
>There is a multiply step instruction. There is no such support for division.
>It can take 200+ cycles to do a division on the SPARC [worst case]. 
>A 32 x 32 bit unsigned multiply takes 45-47 cycles. 

Oh, posh.  A CDC Cyber 170/760 can do a 60x60 -> 60 multiply (fp) in 5
cycles, worst case.  Divide is atrocious, being the only instruction slower
than a load (a load is 26 cycles, but I forget exactly how long a divide
takes).  However, proper instruction ordering means you don't have to worry
too much about how long it takes.  (Multiply is pipelined [does two 30-bit
multiplies at the same time], but divide isn't.  Sequential algorithm, if I
remember correctly.  Apparantly Seymour *hates* divides 8-).)

Just had to plug Seymour 8-).

-- 
Sean Eric Fagan  | "Time has little to do with infinity and jelly donuts."
seanf@sco.COM    |    -- Thomas Magnum (Tom Selleck), _Magnum, P.I._
(408) 458-1422   | Any opinions expressed are my own, not my employers'.