Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!samsung!usc!wuarchive!texbell!attctc!pollux!ti-csl!stafford!tms390!krueger
From: krueger@tms390.Micro.TI.COM (Steve Krueger)
Newsgroups: comp.arch
Subject: Re: Integer Multiply/Divide on Sparc
Summary: SPARC Architecture has integer multiply, TI micros
Message-ID: <377@tms390.Micro.TI.COM>
Date: 28 Dec 89 00:42:24 GMT
References: <84768@linus.UUCP> <8840004@hpfcso.HP.COM> <1804@l.cc.purdue.edu> <1979@eric.mpr.ca>
Organization: Texas Instruments, Houston
Lines: 56

OK, enough already.  I'll tell.

While no SPARC microprocessors to date implement them, there are
integer multiply instructions which have been specified for the SPARC
architecture.  Some (possibly many) future implementations will find
it advantageous to implement them.  They are intended to produce
results in very few cycles on the "fastest" implementations.  Current
implementations and those that don't support these instructions will
trap and presumably emulate the operation.  The multiply step
instruction will remain as well.

Breifly, a little more detail:

Multiply is 32x32 -> 64.  The low order portion of the result goes
into the destination register of the instruction and the high order
part goes into the Y register (same one used by multiply step
instruction).  The instruction comes in signed and unsigned forms and
each may set the condition codes or not.  (All of that is standard for
arithmetic instructions in SPARC.)

There is a similar set of divide instructions that are pretty much the
inverse of the multiply instructions.

In article <1979@eric.mpr.ca>, hui@joplin.mpr.ca (Michael Hui) writes:
> 
> For a frame of reference, T.I.'s DSP chip TMS320C25 does a 16x16
> multiply in a single cycle.

I need to comment on this since I know a little about these chips.

The fastest TMS320C25 is available with an 80nS cycle time and the
'C25 can do multiply and accumulate at that rate.  The 32x32 -> 64
integer multiply that is desired for 32-bit processors is 4 times as
complex as the 16x16 -> 32 in the `C25.  The DSP's allocate a lot of
their chip area to multiply.  GP micros have other priorities and a
full 32x32 -> 64 multiplier array can take {\em serious} Si area.  So
you can expect that DSPs will have better performance/price for
multiply than GP micros.  All of that said, SPARC needs integer
multiply instructions and so it will get them.

BTW, there are several TI parts with higher integer multiply
performance than the `C25.  I don't mean this as a commercial, just
for informational purposes.  The TMS320C50, another integer DSP chip,
was announced last year.  The 'C50 does an integer multiply in 50nS.
A TI floating point datapath chip SN74ACT8847 can also perform integer
multiply.  A 32x32 -> 64 integer multiply takes just 30nS on the 33MHz
version of that chip.  It does pretty well on floating point stuff too :-)
but its not a processor.

	Steve Krueger		krueger@micro.ti.com
	SPARC Applications
	Texas Instruments
	Houston, Texas
	(713) 274-2479

** Mod any actual facts found above, these are my thoughts alone. **