Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Context switching on RISC chips
Message-ID: <1973@crdos1.crd.ge.COM>
Date: 3 Jan 90 17:26:52 GMT
References: <3167@iitmax.IIT.EDU> <28573@amdcad.AMD.COM> <52104@srcsip.UUCP> <5482@bd.sei.cmu.edu>
Organization: GE Corp R&D Center, Schenectady NY
Lines: 24
Reply-exos:@crdgw1:To: davidsen@crdos1.crd.ge.com (bill davidsen)


  While this topic is going on, does any (production) CPU use a register
dirty bit? What I envision is that there would be a load-em-all
instruction which would load all registers from memory and clear the
dirty bits. On context switch the save-em-all instruction would only
save those which were modified.

  I can't envision a system working which didn't preserve the registers
in a context switch, and I think the proposed loop
	sleep a bit
	check the registers
is fanciful. If the registers checge while my process is running I would
expect the process to die rather sooner than later. I *can* envision
that on first startup the registers might not be set to a known state.

  With memory it's another story. We used to allocate memory and search
it all the time in the "good old days." We ran (perhaps crawled) 32
users on a single MB of core, too, and I don't want to go back to that,
either. 
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon