Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!uunet!microsoft!brianw
From: brianw@microsoft.UUCP (Brian WILLOUGHBY)
Newsgroups: comp.sys.apple
Subject: Re: Speedy WDC Chips (was Re: Apple II
Summary: RAM memory access times
Message-ID: <10069@microsoft.UUCP>
Date: 25 Dec 89 07:10:28 GMT
References: <7803.infoapple.net@pro-generic> <675@batman.moravian.EDU> <1989Dec9.071924.16807@ncsuvx.ncsu.edu>
Reply-To: brianw@microsoft.UUCP (Brian WILLOUGHBY)
Organization: Microsoft Corp., Redmond WA
Lines: 86

In article <1989Dec9.071924.16807@ncsuvx.ncsu.edu> rnf@shumv1.ncsu.edu (Rick Fincher) writes:
>
>To get the number of nanoseconds per clock cycle
>divide 1000 ns by cycles in mhz (million cycles per sec).  A 10 mhz processor
>then would have a cycle time of 100 ns.  If you consider that one half 
>of the cycle is used to update the video circuitry, the RAM only has
>half that time to respond, asuming it loads one byte per cycle.  So it has 
>to work twice as fast, ie 50ns. The TransWarp GS doesn't have video circuitry
>but it does have to trasnsfer its RAM contents back to the GS' main memory.
>In the gs running at 2.8 mhz you would think about 357 ns are needed.  But 
>you have to divide that by 2, thus giving your RAM about 178ns to deliver 
>its contents.

You overlooked a few details here.  RAM access times are NOT the total cycle
time, but actually only a small part.  A memory access cycle involves getting
the address to the RAM chip and getting the data back (for reads).  The total
cycle time is always significantly longer than the RAM access time.  For
example, the Apple ][ has a 500ns cycle (after you give half of the 1 MHz cycle
to the video circuitry).  BUT, you can't get an Apple ][ to work with any RAM
chips which are longer than 200ns access time.  The reason for this is the
number of steps involved in accessing dynamic RAM:

Send Row address
wait
Instruct RAM chip to store Row address
wait
Send Column address
wait
Instruct RAM chip to store Column address
wait <-- this is the RAM access time
Transfer data

RAM chips are only rated by the final wait time.  The other wait times are
assumed.  On the Apple ][ they add up to 300ns!

This explains why some processors (68000, 8086) use multiple cycles to access
memory.  The respective designers decided to break up these steps into separate
cycles, while the 6502 designers decided to simply send the address at the
beginning of a cycle and expect the data transfer to occur at the end of the
cycle.

P.S.  I made the exact same mistake (of merely measuring the total processor
cycle time) myself.  Designing a few dynamic RAM memory interfaces tends to
clear things up.

>So dual port RAM is used for the video
>on machines like the 16mhz Mac II.

Actually, the Mac II CPU has no video.  Video cards are used, and since these
are accessed across the NuBus, the controller can happily access its own memory
while the Mac accesses program memory.  There are no conflicts unless the Mac
needs to write to video memory, and then the timings are synchronized.  I just
wanted to point out that not all Mac II video cards have (or need) dual port
RAM.  The Mac SE/030 DOES have dual port video memory because the video
circuitry is built into the main CPU board.  The SE/030 still keeps video and
program memory in separate RAM banks, though.

>The RAM in some of these machines can't work fast
>enough to keep up with the processor, so a wait state has to be thrown in to 
>get good data.  You might wonder why they bother to run the processor at 
>16mhz if the memory can't keep up.  This is done because a lot of operations
>are register to register and don't require memory access, these go at full
>speed.

Some trivia:  I have heard that some (older) PC video cards require 20 wait
states for reads or writes to video!
The original 6 MHz AT required a couple of wait states just for simple
peripheral card accesses.  Depending upon whether the bus access was 8 or 16
bits, the AT's memory cycle was sometimes as slow (500ns) as the 1 MHz Apple
][!
 
>Some of the memory cards on the market for the IIgs require 120ns RAM (the 
>AE cards for example) because they do special things to make sure DMA works 
>for the whole memory range, even for more than 4 rows of chips.

This is related to getting the addressing information to the RAM fast enough.
If there is more memory, the addressing circuitry gets more complicated, and
there are more delays.  Since the Apple memory cycle wont get any longer, you
have to use faster RAM chips to guarantee that the transfer of data occurs in
time.

Brian Willoughby
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