Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!samsung!usc!ucsd!ucbvax!hplabs!hpda!hpcuhb!hpscdc!stout
From: stout@hpscdc.scd.hp.com (Tim Stoutamore)
Newsgroups: comp.sys.apple
Subject: Re: Re: Really small question (a really long explanation)
Message-ID: <5760005@hpscdc.scd.hp.com>
Date: 27 Dec 89 17:46:50 GMT
References: <8916.infoapple.net@pro-generic>
Organization: Hewlett-Packard, Santa Clara Div.
Lines: 1

Sorry for the inadvertent reposting of Brian's message.  I am still just learning the notes system.  Inter-memory moves, whether DMA or MVN/MVP, are constrained to atleast two memory cycles.  This is because one cycle is needed to put the source address on the bus and one cycle is needed to put the destination address on the bus.  The only time that DMA controllers can perform one word per cycle moves is when the transfer is between memory and I/O.