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From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: The Killer Micro From Hell [Really: fight ...
Message-ID: <39807@ames.arc.nasa.gov>
Date: 5 Jan 90 18:09:46 GMT
References: <34030@mips.mips.COM> <4322@nttmhs.ntt.JP>
Sender: usenet@ames.arc.nasa.gov
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In article <4322@nttmhs.ntt.JP> yam@nttmhs.ntt.jp (Toshihiko YAMAKAMI) writes:

>It is interesting to see how fast the KMs are gaining,
>and it is more interesting to find how fast the KMs will be gaining.
>
>I have never touched supercomputers, but I use SONY NEWS with MC68030.

Supercomputing Review recently had an article on the two Cray companies, and
the Cray-3 is planned to have a 2ns clock, with 16 processors.  This information
was stated in the public stock offering prospectus, so it is now public 
knowledge.  This gives an idea of the numbers people are talking about for
the next generation of supercomputers.  500 MHz still compares favorably 
to 50-80MHz numbers for KMs in the same time frame.  The price/performance 
ratio is somewhat different, of course :-)  See below.

Now, many people may differ :-) but *my* rule of thumb for a "good"
implementation (The folks from MIPSCo, Sun, et al. will shoot me for this -
it compresses man years of clever work into a *simplistic* number) is that 
Cray and SPARC tend to produce about .5x clock speed in VAX-equivalent "MIPS" 
(IMHO - this is just a simplistic ballpark figure etc etc your milage may vary)
while MIPSCo tends to be a little better, around .6x or so.  (I guess Crays
tend not to do as well as this on Eugene Brooks favorite code...).

>R6000 runs at 66.7MHz. What is the bottleneck to prevent it

So, I would expect systems to have up to about 40 "MIPS".  An R6280 could
SPECmark, for example, at ~40x an 11/780.  Just my speculation, of course.

>(y) Memory Bandwidth?  What type of CPU starvation is the most critical
>(z) Huting of parallel computation? Superpipeline or superscalar can
>    exploit more parallelism hidden in the codes?
>    Or more sophisticated compilers?
>
>MIPS will release 80MHz version in 1990.

It is interesting to contemplate $100-300K systems, like the SGI Power Series,
with each CPU based on an 80MHz R6000.  The possibility is there for a
system which looks like a Cray scaled down by a factor of about 5 for scalar
work, a factor of 15 for vector work.  At a cost of 1/30 - 1/100.  What would
prevent this from happening?  Memory bandwidth could.  Nobody 
really wants to talk about this in public, but I bet a lot of people are
staying up nights trying to figure out how to scale up memory bandwidth
with processor speed.  Cheaply (If you build it like Cray does, it will
cost like a Cray).

The factor of five could be pretty scary to Cray.  I saw a report summary done
at Livermore a while back in which "4" was the critical speed factor in
which determined whether systems had "significantly different" speed. 

And looking just a little further ahead, an "R9000"
(just making this up out of whole cloth) with a starting clock speed of
100MHz, scaled up to 200 MHz by 1992 or 1993, could put Cray out of business.
SGI will build scalar graphics workstations with half the power of the then
current Crays at 1/100 the cost, and Ardent will do the vector version, with
a similar price advantage.  An amusing idle speculation (?)

Now, about that memory bandwidth?

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117