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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Memory Bandwidth vs. Processor Speed
Message-ID: <34190@mips.mips.COM>
Date: 5 Jan 90 21:12:17 GMT
References: <34030@mips.mips.COM> <4322@nttmhs.ntt.JP> <39807@ames.arc.nasa.gov> <1990Jan5.193511.3879@mintaka.lcs.mit.edu>
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In article <1990Jan5.193511.3879@mintaka.lcs.mit.edu> shaw@au-bon-pain.lcs.mit.edu.UUCP (Andy Shaw) writes:
>Actually, I was under the impression that this was no big secret --
>memory bandwidth and latency are going to be the limiting factors in
>the speed of computer systems (both parallel and serial) of the very
>near future.

>Am I wrong to say "latency" in the same sentence with "bandwidth"?  I
>don't really think that they are separate issues.  I don't think
>anything spectacularly interesting has been done about memory
>bandwidth or latency recently -- registers, caches, and interleaving
>are all old, old ideas ... what else has come around?

Nothing much, except for issues that arise with inexpensive silicon that
sometimes change the tradeoffs in memory system design, i.e., you sometimes
get to do things with page-mode DRAMs that encourage different
organizations than what you would have done with some of the more expensive
older memory systems.  Of course, most micros in general suffer (performance)
from having just 1 path from CPU to memory, compared with supercomputers/
minisupers.

As in the old saw (approx):, "You can buy bandwidth, but latency is forever,
because if you break the laws of physics, God pulls you over
and gives you a speeding ticket, and He cannot be bribed."
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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