Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!usc!polyslo!news
From: news@polyslo.CalPoly.EDU (News Guru)
Newsgroups: comp.arch
Subject: Re: New Moto FP chip
Keywords: TRW CPUAX SuperChip
Message-ID: <25aa6e06.6de@polyslo.CalPoly.EDU>
Date: 9 Jan 90 23:04:38 GMT
References: <579@sagpd1.UUCP> <2413@motaus.UUCP>
Reply-To: mdeale@spica.acs.calpoly.edu.UUCP (Myron Deale)
Organization: Cal Poly State Univ,CSC Dept,San Luis Obispo,CA 93407
Lines: 30


In article <2413@motaus.UUCP> phil@motaus.UUCP (Phil Brownfield) writes:
[stuff deleted]
>
>I know next to nothing about the architecture.  The implementation
>is interesting: 0.5 micron CMOS (yes, 0.5), triple layer metal with
>salicide, 4 million devices, die size 1.59 X 1.49 inches (NOT cm).
>Sorry, I don't know the clock speed.  It's built up of 142 macrocells,
>of which 61 must be functional for the part to work.  A small second
>chip, the "Universal Processor", operates if a macrocell fails,
>dynamically reconfiguring the CPUAX and keeping it functional in
>applications requiring high reliability.  200 SP MFLOPS are claimed.
>
>Phil Brownfield, Motorola Semiconductor
>oakhill!motaus!phil@cs.utexas.edu probably works

An article on this appears in EE Times 1/8/90, p.4, "TRW fabs VHSIC
superchip." I am somewhat troubled by one sentence in the article.
I quote (w/o permission, sorry), "The company achieved 0.5-micron
feature sizes on a high numerical-aperture g-line stepper from Nikon."
[The "company" being Moto ]

Umm, given the recent complaints that the Japanese are taking over
the semiconductor processing equipment market ... I'm wondering
if the US very-high-speed IC program for the DOD is being built
on Japanese technology?   Do I have the right Nikon?


-Myron
// mdeale@cosmos.acs.calpoly.edu