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Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!ubc-cs!fs1!fs0.ee.ubc.ca!vincel
From: vincel@fs0.ee.ubc.ca (vincent li)
Newsgroups: sci.electronics,comp.misc
Subject: Memory access time
Message-ID: <929@fs1.ee.ubc.ca>
Date: 10 Jan 90 19:36:36 GMT
Sender: news@fs1.ee.ubc.ca
Lines: 25

Hello folks. I am developing an expert advisor for my thesis and is confused on
the following piece of knowledge on (static) memory. On most memory data sheets
the *access time* of the data is usually given by two parameters:
tAA - address access time, time when address is valid to data is valid
tACS - chip select access time, time when chip select is asserted to when
data is valid.

These are for the read cycle. So, in calculations, do I use tACS or tAA?
The conclusion I've made is that the chip select usually controls the address
decoding units within the RAM and address decoding cannot begin until the
CS is asserted. The access time is the time when the address into the RAM
start getting decoded to when the valid data from the memory matrix appears
or can appear on the data bus. Thus, I believe you should use the tAA if
CS is asserted BEFORE the address is valid, and use tACS otherwise, but am
not sure.

Basically, if my definition of the access time is correct, then everything
should be straight forward, right?

Thanx for the help.

------------------------------------------------
vincel@ee.ubc.ca           |-) If you study too much your brain will get so heavy
vinceli@triumfcl.bitnet    %-| that it will begin to sag, lodge in the neck, and
                           |-( cut off breathing. -- Mr. Boffo