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From: bob@cbmvax.commodore.com (Bob Raible - LSI Design)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Chip memory bandwidth, graphics modes
Message-ID: <9207@cbmvax.commodore.com>
Date: 4 Jan 90 16:06:28 GMT
References: <8219@cbnewsm.ATT.COM>
Reply-To: bob@cbmvax.commodore.com (Bob Raible - LSI Design)
Organization: Commodore, West Chester, PA
Lines: 11

In reply to the poster that asked why only 6 bitplanes are available to the
user in lores, the answer is that it is only a matter of silicon design tras on DENISE and not a result of chip bandwidth limitations. Unfortunately the
original DENISE(8362) was designed in 1984(or thereabouts) and was fabricated
in 4 micron NMOS technology which was a sort of standard in those days. The
architecture is fully capable of 8 bitplanes and some provision was made for
them (gaps in the register map,etc.). In fact 8 bitplanes in lores DOES use
the samed bandwidth as HIRES 4 bitplanes.

PS: forgive me if I violated some net protocols. I am not a UNIX(TM) type person
and do not get along real well with vi. I thought that a more or less official
answer would be beneficial.