Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!rutgers!cbmvax!danf
From: danf@cbmvax.commodore.com (Dante Fabrizio - PA)
Newsgroups: comp.sys.ibm.pc
Subject: Expansion Bus Interface Spec's for DMA Bus Master
Keywords: DMA BUS MASTER
Message-ID: <9262@cbmvax.commodore.com>
Date: 9 Jan 90 14:32:13 GMT
Reply-To: danf@cbmvax.commodore.com (Dante Fabrizio - PA)
Organization: Commodore, West Chester, PA
Lines: 7

Can anyone recommend a detailed reference of specifications of the signals 
on a pc AT compatible expansion bus for DMA BUS Master interfacing techniques. 
I have the technical reference manual but, only general signal desriptions are 
covered.
I need to know how to decode REFRESH so I don't conflict with memory refresh
cycle. Are there any good books or sources of timing diagrams available? Please
email any responses.