Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.sys.m88k Subject: Re: Information wanted on m88000 Risc workstations Keywords: 80386 m88000 Everex Opus UNIX DOS Message-ID: <34320@mips.mips.COM> Date: 10 Jan 90 09:07:15 GMT References: <641@s5.Morgan.COM< <25A64468.11498@paris.ics.uci.edu> <648@s5.Morgan.COM> <6915@pdn.paradyne.com> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 95 I don't usually comment in this newsgroup, but there was enough (mis)information in the following that I had to comment: In article <6915@pdn.paradyne.com> alan@oz.paradyne.com (Alan Lovejoy) writes: >Double precision FP is slow primarily because the 88k does not have 64-bit data >paths internally. That is the price Moto paid for putting the FPU on the same >chip as the IPU. The benefits they get are: 1) no need to shuffle data between >integer and fp registers; 2) standardized fp instruction set; 3) assurance for >SW developers that all 88k systems will have HW FP, and 4) you can buy 1 88100 >and 2 88200's at 16MHz for $499 (in lots of 1000, of course); try matching that >price/performance ratio with ANY other CPU. Also, they started out several >years behind MIPS with the Rx000 and 9 months behind SPARC. They are now in >production with 33MHz CMOS parts; MIPS and the SPARC gang are not. They paid a price to put it on the same chip, and it's a legitimate choice, however: 2) MIPS and SPARC certainly have standardized instruction sets. 3) MIPS (at least) supports complete IEEE emulation in the UNIX kernel, so one does not need extra flavors of binaries. 4) Try matching that price/performance: You can put together the core of of a system of similar performance, including CPU, FPU, MMU ,128K caches, glue, for about $400, or less [i've heard of one, which was in large quantities, as low as $250, although that might have been a little slower]. Things like the IDT 3001 reduce the cost even more, and having less cache helps too. a) For some kinds of algorithms, you'd really like more FP regs, which MIPS, SPARC, HP PA have. b) As it stands, with the natural 32-bit organization of the register file, you either: 1) Need more cycles to read/write operands [what 88K did] OR 2) Need more read and write ports, especially to accomadate mulitple-cycle operations whose results come back later. one of the reasons MOST people have separate FP and integer registers is to: 1) organize FP as 64-bit. 2) Have more read and write ports to accommodate heavily-overlapped FP operations. Ports cost, sooner or later. Sun & Solbourne are shipping (SPARC) systems at 33Mhz; Stardent shipping (MIPS) at 32Mhz (to be fair, all just recently). I have no idea how many there are of these things, as I haven't tried to buy them lately. If there are lots of 33Mhz 88Ks actually shipping out there in systems, we haven't seen them, although they certainly exist, and have been benchmarked. Needless to say, always measure performance on real programs, not clock rate: if only clock rate counted, 50Mhz 68030s would be ahead of all other chips mentioned (and they're not). > >Moto is obviously aiming the 88k at the mass market as a direct replacement >of the 68k. MIPS is aiming at the very high end (for example, with the I'm not privy to Moto's plans and aims, but this is a clear statement of MIPS' direction...which is 100% wrong, and why I posted this. Many MIPS chips go into embedded control, laser printers, telephone switches, avionics, autos, etc) for example, and if we can't get to the lowest part of that, we're sure interested in the high- performance part, as well as workstations, and small servers. We do high-end (R6000) besides, but why does that make anybody think we're disinterested in the low-end? MIPS partners who do a lot of embedded say they fight all of the time with Intel 960s, sometimes with 29Ks, and seldom with the 88K.... (now, that's anecdote, and hard to check, but...) >R6000). The next generation of the 88k will be aimed at the high end, while >the current generation will be priced to capture the low and medium market >segments. There is nothing in the 88k architecture to prevent Motorola from Well, they'll have to get the prices down to beat what you can do with standard SRAMs and on-chip cache control. and it's going to be real tough for the part of the embedded market that doesn't care about FP, because people can sell equivalent-performance chipsets for about half the price. >using 64 (or even 128) bit data paths and superscalar pipelining in the >next generation 88k. Should happen within the next year and a half, probably >sooner rather than later (the current generation is almost two years old now, >after all.) I don't think that the competition will be able to match Moto's Where does 2 years come from? Do you count announcements? It is well-known that until about 6-8 months ago, nobody could even ship production systems, due to the crippling FP bugs that only got fixed then. >prices on the current generation. But who knows? The combined register set, as described above, will not help superscalaring much.... "But who knows?": lots of people. Note that there's an awful lot of misinformation and speculation floating around here, presented authoritatively. Of use, when they appear, will be the next set of SPEC numbers, which help give a more realistic assessment of performance than the (increasingly unreliable/gimmickable) *stones. Anyway, the 88K is a credible and respectable chipset, but claims like "it costs $X and nothing else is close" (without giving any data from anything else), and claims of "wonderful things will happen soon, and no one else could match them" are marketing claims, not technical ones. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086