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From: chris@mimsy.umd.edu (Chris Torek)
Newsgroups: comp.unix.questions,comp.unix.wizards
Subject: Re: SCSI Questions
Message-ID: <21804@mimsy.umd.edu>
Date: 13 Jan 90 01:20:46 GMT
References: <1990Jan8.180709.3440@uunet!unhd>
Distribution: comp
Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742
Lines: 30

In article <1990Jan8.180709.3440@uunet!unhd> rg@uunet!unhd (Roger Gonzalez)
writes:
>In the SCSI spec, they say that the target controls the C/D, MSG, and
>I/O bits.  Fine.  In this case, why is there a "target control register"
>on the chip, which in the code examples I have, is used by the initiator
>to "Assert C/D, I/O, or MSG".

As someone else pointed out, this is because the 5380 can act as either
initiator or target.

>In the spec, they say things like "wait one bus settle delay".  Does
>this kind of picky solder-jockey timing become an issue for me as a
>programmer?

This depends on the chip (and sometimes on the glue logic connecting
it to its bus).  With cheap hardware, you have to delay in software.
This is not so bad if the delays are short.  It becomes a real problem
when you have to write

	foodev->foo_csr = FOO_SETUP;
	DELAY(12000);		/* wait ~12 milliseconds */
	foodev->foo_csr = FOO_SETUP | FOO_GO;
	DELAY(1000);		/* another millisecond */
	foodev->foo_csr = FOO_GO;

This is when you wish whoever built the thing had handled the `set up
and go' case directly. . . .
-- 
In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163)
Domain:	chris@cs.umd.edu	Path:	uunet!mimsy!chris