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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: IBM 370 Operand Alignment
Message-ID: <35321@mips.mips.COM>
Date: 1 Feb 90 06:51:37 GMT
References: <9001250026.AA00720@ucbvax.Berkeley.EDU> <35102@mips.mips.COM> <3204@aimt.UU.NET> <3427@odin.SGI.COM>
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Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
Lines: 27

In article <3427@odin.SGI.COM> pkr@maddog.sgi.com (Phil Ronzone) writes:
>In article <3204@aimt.UU.NET> phil@aimt.UU.NET (Phil Gustafson) writes:
>>Dealing with TRANSLATE AND TEST and the even more barouque EDIT AND MARK
>>left me very receptive to the idea of RISC.
>
>Yeah - EDIT AND MARK took almost 14% of the entire microcode memory for
>that one instruction (360/65). And the 360/91, a hardwired non-microcoded
>machine (mostly) didn't support it or any of the other packed decimal
>instructions.

A relevant analysis can be found inGordon Bell & Allen Newell's "Computer
Structures: Readings and Examples", McGraw-Hill, 1971.  In particular,
pages 561-587 look at the S/360 family, and examine tradeoffs and
cost/performance comparisons.  In particular, the hardwired 360/91
had  good cost/performance characteristics, but the best of all was the 
(hardwired) 360/44, which also lacked the variable-length instructions.
ALso, the 360/91 (which had REAL scoreboarding, and was extermely complex,
was shortly withdrawn from the market in favor of the 360/85, which if
not the first, was certainly one of the earliest systems to use
a cache memory.  This is a very useful chapter in many ways, as it also
shows the methods used at the time to scale the same ISA across
technologies.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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