Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!brutus.cs.uiuc.edu!wuarchive!texbell!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.arch Subject: Re: RISC Machine Data Structure Word Alignment Problems? Message-ID: <4YG1638xds13@ficc.uu.net> Date: 1 Feb 90 18:37:38 GMT References: <111@melpar.UUCP> <1990Jan21.224826.1699@esegue.segue.boston.ma.us> <1871@l.cc.purdue.edu> <3428@odin.SGI.COM> Reply-To: peter@ficc.uu.net (Peter da Silva) Organization: Xenix Support, FICC Lines: 17 In article <3428@odin.SGI.COM> pkr@maddog.sgi.com (Phil Ronzone) writes: > No, I disagree. Most of the time the data (mis)alignments are from real world > constraint. Compressed video data, even when capacious CD-ROMs are used, are > full of adjacent 1, 2, 3, and 4 byte integer And ajacent 4-, 5-, 6-, and 12- bit integers as well. I've heard of bit addressible memory, but outside of microcontrollers I've never actually seen it. > And generally you want to > read and display that data as fast as is possible. Having a microcoded > unaligned data capability is faster than user-level instructions doing the > same thing. If your loop is in an instruction cache you'll probably find that your actual memory accesses are coming as fast as the bus can fill them. Cutting the size of your loop will just add wait states. -- _--_|\ Peter da Silva. +1 713 274 5180. . / \ \_.--._/ Xenix Support -- it's not just a job, it's an adventure! v "Have you hugged your wolf today?" `-_-'