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From: cet1@cl.cam.ac.uk (C.E. Thompson)
Newsgroups: comp.arch
Subject: Re: 370 Operand Alignment and Page Faults
Message-ID: <1746@gannet.cl.cam.ac.uk>
Date: 1 Feb 90 15:18:48 GMT
References: <9001270059.AA26776@ucbvax.Berkeley.EDU> <49365@sgi.sgi.com>
Sender: news@cl.cam.ac.uk
Reply-To: cet1@cl.cam.ac.uk (C.E. Thompson)
Organization: U of Cambridge Comp Lab, UK
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In article <49365@sgi.sgi.com> rpw3@rigden.UUCP (Robert P. Warnock) writes:
>On a related issue, my understanding was (from idle conversation with
>some IBM guys several years ago) that the 370 architecture needs at
>least 8 elements in its TLB, and that the TLB must be *at least* 4-way
>set-associative. The reason is some instruction which copies a source to
>a destination while referring to a table (some version of Translate-And-Test
>maybe?). Anyway, the idea was that if the instruction, the source, the
>destination, and the table entry being used all span pages, then you need
>at least 8 valid entries in the TLB to make progress on the instruction.
>
>(Note: I didn't say to *finish* the instruction, I said "make progress".
>If the count were larger than a page size you could hit the same problems
>at the next page boundary. But after handling potential TLB faults [which
>cold cause page faults] you would eventually begin to make progress again.)
>
>Has anyone got a more exact reference with the details of the "worst case"?
>What *is* the absolute minimum size of TLB a 370 or a 30xx needs? How big
>are the actual TLBs in real machines?

In the 370 architecture the TLB is loaded by "hardware", not software, so
not all the entries needed to complete a (non-interruptible) instruction
need be present in the TLB at one time (though this might be a requirement
in some models). However, it is certainly true that all the relevant pages
must be in store, and the page table entries marked "valid". And yes, the
critical number is eight: a 4-byte EXECUTE instruction might cross a page
boundary; its subject instruction might also do so; and it might be an SS
instruction (e.g. MVC) whose source and destination operands both crossed
page boundaries; and all these pages could be different (indeed, they could
all be in different segments). The page table entries themselves are not
accessed by virtual but by real addresses, so they are not relevant in this
context. (There is a possible extra complication in SIE mode under 370/XA,
when the virtual machine's page zero - real to the guest, but virtual to
the host - may also need to be accessible.)

As regards interruptible instructions, it is sufficient, as you say, that
the instruction be able to "make progress" with eight valid page table
entries. In this context, it is significant that those of the 3090 vector
facility instructions that access non-contiguous vector operands have the
guarantee "access exceptions are not recognized more than seven element
locations beyond the current one" (SA22-7125-3 p.2-24).

Chris Thompson
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