Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!usc!ucsd!ames!ames.arc.nasa.gov!lamaster From: lamaster@ames.arc.nasa.gov (Hugh LaMaster) Newsgroups: comp.arch Subject: Re: RISC Machine Data Structure Word Alignment Problems? Message-ID: <41933@ames.arc.nasa.gov> Date: 2 Feb 90 16:33:04 GMT References: <111@melpar.UUCP> <1990Jan21.224826.1699@esegue.segue.boston.ma.us> <1871@l.cc.purdue.edu> <3428@odin.SGI.COM> <4YG1638xds13@ficc.uu.net> Sender: usenet@ames.arc.nasa.gov Organization: NASA - Ames Research Center Lines: 27 In article <4YG1638xds13@ficc.uu.net> peter@ficc.uu.net (Peter da Silva) writes: >And ajacent 4-, 5-, 6-, and 12- bit integers as well. I've heard of bit >addressible memory, but outside of microcontrollers I've never actually >seen it. The CDC STAR and its relatives (Cyber 205, ETA 10) all have/had bit addressable memory. I think it is a good idea. On the subject of this discussion, those machines *still* required alignment on natural boundaries. Bits on bits (easy :-) bytes on bytes, 32 bit on 32 bit, 64 bit on 64 bit, etc. I note that the machine had 48 bit addresses, breaking the 32 bit addressing boundary almost 20 years ago. Of course, the machine supported 64 bit registers (both 32 and 64 actually). On the other subject of this discussion, the System Programming Language for those machines had a special construct to be used when you needed to create packed structures. Other languages do too. It is not correct to assume that you can create an arbitrary structure and expect that the compiler will map it in a certain way in memory. You need a special construct to do that. Thank goodness (almost) nobody builds 36 bit, 48 bit, and 60 bit machines anymore- you might even be able to do it in a portable way. Hugh LaMaster, m/s 233-9, UUCP ames!lamaster NASA Ames Research Center ARPA lamaster@ames.arc.nasa.gov Moffett Field, CA 94035 Phone: (415)694-6117