Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!rpi!brutus.cs.uiuc.edu!uakari.primate.wisc.edu!ames!sgi!shinobu!odin!maddog!pkr From: pkr@maddog.sgi.com (Phil Ronzone) Newsgroups: comp.arch Subject: Re: RISC Machine Data Structure Word Alignment Problems? Message-ID: <3518@odin.SGI.COM> Date: 2 Feb 90 19:12:27 GMT References: <111@melpar.UUCP> <1990Jan21.224826.1699@esegue.segue.boston.ma.us> <1871@l.cc.purdue.edu> <3428@odin.SGI.COM> Sender: news@odin.SGI.COM Organization: Silicon Graphics, Inc., Mountain View, CA Lines: 23 In article aglew@dwarfs.csg.uiuc.edu (Andy Glew) writes: >>Having a microcoded unaligned data capability is faster than >>user-level instructions doing the same thing. > >Why? > >Microcoded unaligned data takes two cycles to load an unaligned datum. >(Assuming the unaligned datum overlaps two data bus widths.) MIPSco >style load-left and load-right take two cycles to load the same >unaligned datum. I was thinking of bus-wide words (i.e., typically 32-bits). You have at least: BUS FETCH / SHIFT ALIGN / BUS FETCH / SHIFT ALIGN / OR / STORE Implementing these at typical user level adds even more -- tests to figure out how much to shift etc. ------Me and my dyslexic keyboard---------------------------------------------- Phil Ronzone Manager Secure UNIX pkr@sgi.COM {decwrl,sun}!sgi!pkr Silicon Graphics, Inc. "I never vote, it only encourages 'em ..." -----In honor of Minas, no spell checker was run on this posting---------------