Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!mitel!sce!greg
From: greg@sce.carleton.ca (Greg Franks)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Message-ID: <771@sce.carleton.ca>
Date: 31 Jan 90 16:18:41 GMT
References: <3300098@m.cs.uiuc.edu>
Reply-To: greg@sce.UUCP (Greg Franks)
Organization: Systems Eng., Carleton Univ., Ottawa, Canada
Lines: 29

In article <3300098@m.cs.uiuc.edu> gillies@m.cs.uiuc.edu writes:
>
>Here's a rhetorical question:
>
>When was the last time someone introduced a new CISC architecture?
>How many years has it been?  New versions of old chips ('486, '040,
>etc) do not count as "new architectures".

The big players in the microprocessor wars are busy souping up their
existing CISC processors all of the time, so why would they bother
concocting new ones.  People sure like having the latest CPU on their
desk to run lotus 123 or MacDraw.  Furthermore, with the lastest CISC
processors reaching into the domain of the RISC processors in terms of
performance (eg, 68040 @ 25 MHz being faster than SPARC @ 25 MHz
according to Byte), who needs most of the RISC processors floating
around these days?  Just imagine, 100MIPs and the ability to run an
anchient version Word Perfect all in one box!

Introducing *any* new architecture, be it RISC or CISC, is likely
going to be exceptionally difficult these days unless that processor
can demonstrate clear superiority over all others in some way or
another (perhaps a cray-on-a-chip??)

Sign me - I want an upgrade :-)
-- 
Greg Franks   (613) 788-5726     Carleton University,             
uunet!mitel!sce!greg (uucp)  	 Ottawa, Ontario, Canada  K1S 5B6.
greg@sce.carleton.ca (bitnet)	 (we're on the internet too. (finally))
Overwhelm them with the small bugs so that they don't see the big ones.