Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!brutus.cs.uiuc.edu!lll-winken!ames!pacbell!trane!thomas
From: thomas@trane.UUCP (Thomas Driemeyer)
Newsgroups: comp.arch
Subject: Re: 68040
Keywords: need data
Message-ID: <851@trane.UUCP>
Date: 2 Feb 90 22:48:23 GMT
Organization: Aurora Systems Redwood City, California
Lines: 25


In <3426@odin.SGI.COM>, pkr@maddog.sgi.com (Phil Ronzone) writes:
> And the doubling of the RAM banks from 2 to 4 eats a lot of real estate
> (remember, the 68040 has a 64-bit bus) and gives a few NuBus problems.

You appear to know a lot more about the 68040 than I do. I haven't seen
a data book yet, but I am interested in this chip. Could someone please
post some data?

Some of my questions are, does it have dynamic bus sizing? Is that 64-bit
bus actually two busses, I/D, or is it a wider path to the caches? Does it
support burst cache fills? How fast is the fpu? If it really has a six-
stage pipeline, how does it deal with branches? I assume its user mode is
100% compatible to the 68020/30, so branch prediction and delay slots are
out. Does it still have micro/nanocode, other than for complex fpu ops?
User context is some 150 bytes, do registers have dirty bits or something?

And the most difficult one: When will it be available, and how much will
it cost?

Thanks!


Thomas Driemeyer
pyramid!trane!thomas