Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!usc!polyslo!jdudeck
From: jdudeck@polyslo.CalPoly.EDU (John R. Dudeck)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Message-ID: <25cb6b65.702c@polyslo.CalPoly.EDU>
Date: 3 Feb 90 23:38:13 GMT
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM>
Reply-To: jdudeck@polyslo.CalPoly.EDU (John R. Dudeck)
Organization: Cal Poly State University -- San Luis Obispo
Lines: 16


In article <35456@mips.mips.COM> mash@mips.COM (John Mashey) writes:
>a 68040 @ 25Mhz to be faster than a SPARC @ 25Mhz?
>(yes, I've seen the Motorola ads that show the 68040 to be 20 mips versus
>a SPARC's 18.... :-) 

In my understanding of RISC vs CISC, you can't directly compare RISC MIPS
against CISC MIPS, because the risc instructions are simple, whereas the
cisc instructions are complex.  It may take several risc instructions to
perform one cisc instruction.  Originally the trick was to get the several
risc instructions to execute in less time than the one complex instruction.
Now the tables are turned, because the cpu designers have figured out
how to get the cisc chips to perform the complex instruction in the same clock
cycle that the risc chip takes to perform the simple instruction...  In
a DEC Professional editorial I saw the expression CRISCO (complex risc)
architecture to refer to this.

-- 
John Dudeck                           "You want to read the code closely..." 
jdudeck@Polyslo.CalPoly.Edu             -- C. Staley, in OS course, teaching 
ESL: 62013975 Tel: 805-545-9549          Tanenbaum's MINIX operating system.