Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uakari.primate.wisc.edu!ames!decwrl!orc!mipos3!blabla!kds From: kds@blabla.intel.com (Ken Shoemaker) Newsgroups: comp.arch Subject: Re: Handling mis-alignment (was Re: RISC Machine Data Structure Word Alignment Problems? Message-ID: <1577@mipos3.intel.com> Date: 3 Feb 90 23:38:09 GMT References: <3428@odin.SGI.COM> <2038@bnr-rsc.UUCP> Sender: news@mipos3.intel.com Reply-To: kds@blabla.UUCP (Ken Shoemaker) Organization: Santa Clara Microprocessor Division, Intel Corp., Santa Clara, CA Lines: 24 The i486 handles misaligned transfers transparently from the programming standpoint. From a performance standpoint, there is no penalty for aligned transfers, for misaligned transfers a misaligned transfer adds two clocks to the two transfers that need to be performed to get the data. Thus, for all cache hits, an aligned load takes 1 clock while a misaligned load takes 4 clocks (2 + 1 for each transfer). The two clocks are a "false start clock" for the transfer that gets aborted (since split processing is required) and a "tickle" cycle that insures that before any data transfer is attempted that the whole object is addressable. Thus, no transfer for a memory object will be seen on the pins until the processor has determined that it can retrieve both parts. In addition, the i486 has the ability to force traps on all misaligned transfers. This lets people insure that the data structures for their programs are such that they are getting the highest performance from their machines and also insures that their data structures are portable with mathines that don't support misaligned transfers (assuming, of course, that the hardware supported representation of objects is the same in memory). This facility is provided through a bit in control register 0, which, by default, allows misaligned objects. ---------- Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California csnet/arpanet: kds@mipos2.intel.com uucp: ...{hplabs|decwrl|pur-ee|hacgate|oliveb}!intelca!mipos3!kds