Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!apple!rutgers!mephisto!udel!rochester!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay
From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Summary: RISC wins
Message-ID: <7826@pt.cs.cmu.edu>
Date: 4 Feb 90 03:40:26 GMT
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU>
Organization: Carnegie-Mellon University, CS/RI
Lines: 35

In article <25cb6b65.702c@polyslo.CalPoly.EDU> jdudeck@polyslo.CalPoly.EDU
	 (John R. Dudeck) writes:
>In my understanding of RISC vs CISC, you can't directly compare RISC MIPS
>against CISC MIPS, because the risc instructions are simple, whereas the
>cisc instructions are complex.  It may take several risc instructions to
>perform one cisc instruction.  Originally the trick was to get the several
>risc instructions to execute in less time than the one complex instruction.
>Now the tables are turned, because the cpu designers have figured out
>how to get the cisc chips to perform the complex instruction in the same clock
>cycle that the risc chip takes to perform the simple instruction...  

I think that this overstates the advantage of CISC. The recent CISC
chips aren't getting a complex instruction to run in one clock. More
correctly, they are getting the most commonly used simple
instructions to run in one clock. They are also getting the most
commonly used complex instructions to run in fewer clocks. 

The whole RISC thing came about because several compiler people found
that they could get better performance out of CISCs by ignoring many
of the complex instructions, thus treating the machines as RISC.  The
hardware people responded by building machines that did only the
simple things. To my surprise, the payoff was fairly big.

RISC reduced the design time - an advantage that a fast CISC doesn't
have. It also reduced the silicon area, but as all the players add
onchip caches and whatnot, that matters little.  Finally, RISC
increased the clock rate, but advanced CISC should come close.

So, is it a wash? More-or-less, yes - if RISC designs stand still.
But they aren't. RISC is moving to ECL and GaAs, where transistors
are scarce. They are also moving to superscalar designs, where the
RISC/CISC difference is between incredible complexity and stupefying
complexity.
-- 
Don		D.C.Lindsay 	Carnegie Mellon Computer Science