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From: pkr@maddog.sgi.com (Phil Ronzone)
Newsgroups: comp.arch
Subject: Re: 370 Operand Alignment and Page Faults
Message-ID: <3561@odin.SGI.COM>
Date: 4 Feb 90 07:54:27 GMT
References: <9001270059.AA26776@ucbvax.Berkeley.EDU> <49365@sgi.sgi.com>
Sender: news@odin.SGI.COM
Organization: Silicon Graphics, Inc., Mountain View, CA
Lines: 28

In article <49365@sgi.sgi.com> rpw3@rigden.UUCP (Robert P. Warnock) writes:
>In article <9001270059.AA26776@ucbvax.Berkeley.EDU> JOSH@IBM.COM ("Josh
>On a related issue, my understanding was (from idle conversation with
>some IBM guys several years ago) that the 370 architecture needs at
>least 8 elements in its TLB, and that the TLB must be *at least* 4-way
>set-associative. The reason is some instruction which copies a source to
>a destination while referring to a table (some version of Translate-And-Test
>maybe?). Anyway, the idea was that if the instruction, the source, the
>destination, and the table entry being used all span pages, then you need
>at least 8 valid entries in the TLB to make progress on the instruction.
>
>(Note: I didn't say to *finish* the instruction, I said "make progress".
>If the count were larger than a page size you could hit the same problems
>at the next page boundary. But after handling potential TLB faults [which
>cold cause page faults] you would eventually begin to make progress again.)

The 370 could get by with zero TLB elements. The 370 does NOT fault on
any TLB operation. The segment and page tables are chased in memory and
must be in memory at all times (not paged out). The original small
370's had 8 elements, later 16, and the bigger 370's had 128.

The 360/67 also had 8 in the "Blauuw box".


------Me and my dyslexic keyboard----------------------------------------------
Phil Ronzone   Manager Secure UNIX           pkr@sgi.COM   {decwrl,sun}!sgi!pkr
Silicon Graphics, Inc.               "I never vote, it only encourages 'em ..."
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