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From: pkr@maddog.sgi.com (Phil Ronzone)
Newsgroups: comp.arch
Subject: Re: CISC Silent Spring
Message-ID: <3562@odin.SGI.COM>
Date: 4 Feb 90 08:16:48 GMT
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <7826@pt.cs.cmu.edu>
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In article <7826@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
>RISC reduced the design time - an advantage that a fast CISC doesn't
>have. It also reduced the silicon area, but as all the players add
>onchip caches and whatnot, that matters little.  Finally, RISC
>increased the clock rate, but advanced CISC should come close.
>
>So, is it a wash? More-or-less, yes - if RISC designs stand still.
>But they aren't. RISC is moving to ECL and GaAs, where transistors
>are scarce. They are also moving to superscalar designs, where the
>RISC/CISC difference is between incredible complexity and stupefying
>complexity.

I see that as the ONLY large advantage that RISC has. It simply has
been able to reduce the design time.

The second argument (gate scarcity) is interesting, but does it not
also have a limit? If gates are "typical" in the 10,000-100,000 range,
yes, but how about when gates are "typical" in the 1,000,000-10,000,000.


------Me and my dyslexic keyboard----------------------------------------------
Phil Ronzone   Manager Secure UNIX           pkr@sgi.COM   {decwrl,sun}!sgi!pkr
Silicon Graphics, Inc.               "I never vote, it only encourages 'em ..."
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