Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: CISC Silent Spring
Message-ID: <1990Feb5.211208.15741@utzoo.uucp>
Organization: U of Toronto Zoology
References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU>
Date: Mon, 5 Feb 90 21:12:08 GMT

In article <25cb6b65.702c@polyslo.CalPoly.EDU> jdudeck@polyslo.CalPoly.EDU (John R. Dudeck) writes:
>Now the tables are turned, because the cpu designers have figured out
>how to get the cisc chips to perform the complex instruction in the same clock
>cycle that the risc chip takes to perform the simple instruction...

No, they've figured out how to make tomorrow's CISC chips perform the
simpler instructions in the same clock cycle that yesterday's RISC chips
took to perform similarly simple operations.  The complicated instructions
are still slow (and still rarely used), the RISCs still have a built-in
lead due to shorter design times, and the CISCs still have a built-in
handicap due to the mass of instruction/decoding/exception baggage
dragging along behind their RISC-like cores.
-- 
SVR4:  every feature you ever |     Henry Spencer at U of Toronto Zoology
wanted, and plenty you didn't.| uunet!attcan!utzoo!henry henry@zoo.toronto.edu