Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@dwarfs.csg.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: RISC Machine Data Structure Word Alignment Problems? Message-ID: Date: 5 Feb 90 15:42:27 GMT References: <111@melpar.UUCP> <1990Jan21.224826.1699@esegue.segue.boston.ma.us> <1871@l.cc.purdue.edu> <3428@odin.SGI.COM> <3518@odin.SGI.COM> Sender: news@ux1.cso.uiuc.edu (News) Organization: University of Illinois, Computer Systems Group Lines: 21 In-Reply-To: pkr@maddog.sgi.com's message of 2 Feb 90 19:12:27 GMT >>>Having a microcoded unaligned data capability is faster than >>>user-level instructions doing the same thing. >> >>Microcoded unaligned data takes two cycles to load an unaligned datum. >>(Assuming the unaligned datum overlaps two data bus widths.) MIPSco >>style load-left and load-right take two cycles to load the same >>unaligned datum. > >I was thinking of bus-wide words (i.e., typically 32-bits). >You have at least: > BUS FETCH / SHIFT ALIGN / BUS FETCH / SHIFT ALIGN / OR / STORE >Implementing these at typical user level adds even more -- tests to >figure out how much to shift etc. LWL/LWR seem to work this way (and the MIPSco folk will correct me, I'm sure): BUS FETCH / SHIFT ALIGN / STORE selected bytes - LWL BUS FETCH / SHIFT ALIGN / STORE selected bytes - LWR Two instructions. Cycles depending on mermory. -- Andy Glew, aglew@uiuc.edu