Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!zephyr.ens.tek.com!uw-beaver!uw-entropy!quick!srg
From: srg@quick.COM (Spencer Garrett)
Newsgroups: comp.arch
Subject: Re: 68040
Keywords: need data
Message-ID: <7793@quick.COM>
Date: 5 Feb 90 21:16:45 GMT
References: <851@trane.UUCP>
Organization: Quicksilver Engineering, Seattle
Lines: 39

> Some of my questions are, does it have dynamic bus sizing?
	Nope.  That's one of the major differences between
	the 680[23]0 and the 68040 bus.
> Is that 64-bit bus actually two busses, I/D,
> or is it a wider path to the caches?
	The external bus is 32 bits, but there are separate
	I and D caches on the chip, and the instruction unit
	uses Harvard Architecture (ie - separate I/D busses).
> Does it support burst cache fills?
	It much prefers them.
> How fast is the fpu?
	Supposedly quite fast for the operations it supports, but
	I don't have any actual numbers.  The 68040 fpu only does
	add, sub, mul, div, cmp, abs, neg, and sqrt, though it does
	all the data type combinations for the above.  Everything
	else traps and gets emulated in software.
> If it really has a six-stage pipeline, how does it deal with branches?
> I assume its user mode is 100% compatible to the 68020/30,
> so branch prediction and delay slots are out.
	I don't know the details here, but all exceptions are precise,
	and I don't think there's any out-of-order execution.  It is
	fully compatible with its predecessors in user mode,
	and even nearly compatible in supervisor mode.
> Does it still have micro/nanocode, other than for complex fpu ops?
	I don't know for sure, but I'd bet there's no nanocode, and
	probably not much microcode.  The only "complex" fpu op is
	sqrt, so maybe they bit the bullet and hardwired it all.
> User context is some 150 bytes, do registers have dirty bits or something?
	User context varies depending upon the source of irritation.
	For a "normal" context swap (supervisor mode entered by interrupt
	or trap) the integer unit state is 8 bytes on the stack and
	64 bytes of registers.  Fpu state is 4 bytes if you haven't
	used the fpu since it was last reset or 100 bytes if you're
	using it but it isn't unhappy at the moment.  A faulting
	instruction will generate considerably more context, but
	those are (hopefully) rare.
> And the most difficult one: When will it be available, and how much will
> it cost?
	I'm hearing summer and $750.