Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: 68040
Message-ID: <1990Feb6.193714.20898@utzoo.uucp>
Organization: U of Toronto Zoology
References: <851@trane.UUCP> <7793@quick.COM> <5120@crdgw1.crd.ge.com>
Date: Tue, 6 Feb 90 19:37:14 GMT

In article <5120@crdgw1.crd.ge.com> oconnordm@CRD.GE.COM (Dennis M. O'Connor) writes:
>] 	... The only "complex" fpu op is sqrt...
>
>Sqrt is not much more complex than division, actually. Look at
>the manual procedures you were taught for each : very similar.
>I think I've seen array circuit designs that did mul, div and sqrt. 

The IBM 801 people mentioned in one paper that one reason they liked having
a divide-step instruction rather than a full divide was that a carefully-
designed divide-step could double as a sqrt-step.

The IEEE floating-point folks thought sufficiently highly of the utility
of sqrt, and sufficiently lowly :-) of its complexity compared to divide,
that it's a required operation for an IEEE FP implementation.  Looks like
the 040's FP box implements exactly what's needed for IEEE conformance,
in fact.
-- 
SVR4:  every feature you ever |     Henry Spencer at U of Toronto Zoology
wanted, and plenty you didn't.| uunet!attcan!utzoo!henry henry@zoo.toronto.edu