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From: piaw@cory.Berkeley.EDU (Na Choon Piaw)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: 68040 vs RISC
Message-ID: <21699@pasteur.Berkeley.EDU>
Date: 2 Feb 90 18:26:29 GMT
References: <1990Feb2.073513.29698@agate.berkeley.edu>
Sender: news@pasteur.Berkeley.EDU
Reply-To: lachesis@nyquist.bellcore.com
Distribution: usa
Organization: Bell communications research
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In article <1990Feb2.073513.29698@agate.berkeley.edu> laba-3en@web-1c (Raja S Kushalnagar) writes:
>The Motorola 68040, if what I've been reading about here is to be believed,
>has almost been able to surmount the difficulties of deep pipelining, though
>it seems not to have surmounted the issue of efficient window register 
>meshing, and probably might not be able to get over it at all, unless it 
>goes more the RISC way, which it already seems to be going towards, but while
>retaining all the advantages of CISCs.  If that can be done, it should really

I beg to differ.  During a study of MIPS vs. RISC by DEC's WRL, it was found
that a better compiler will *always* do better for code by using a large
register set instead of wasting all that register space using a register
window system.  In fact, the prime reason why Berkeley did the RISC with
register windows was that the team producing the RISC and RISC II did not
include compiler experts.  So, the 680x0 series could improve by adding more
registers, and improving compiler technology (especially register
allocation) to take advantage of those registers (as was done with the MIPS).

The problem with a large register file is that when a context switch occurs,
the enter file has to be dumped.  Also, the nesting level of functions,
should they exceed the (typically small) register window nesting level, will
cause an overflow and require a complete dump of all the register windows.
According to the WRL report (which I can't quote from since I don't have it
with me, see the technical report: Register allocation versus Register
windows by Digital Equipment Corp. Western Research Labs), this causes such
a performance penalty that MIPS, with its better compilers, came out
significantly faster.

In fact, with the advent of portable compilers, I'd warrant that it'll be
cheaper in the long run.  (Just do the compiler once)

>RISC seems to be somewhat superior, given the current technological and 
>economic constraints.  It seems a bit shaky though. 

RISC is not shaky.  Given the current technology, it is probably the only
architecture capable of being implemented on the latest (highest speed)
technologies like GaAr.

>	Raja.

lachesis@nyquist.bellcore.com

"Atari might not have done better [than C=] had they bought Amiga, but they
couldn't have done much worse, either."