Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!psuvax1!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: 68040 vs RISC
Message-ID: <9591@cbmvax.commodore.com>
Date: 2 Feb 90 23:32:49 GMT
References: <1990Feb2.073513.29698@agate.berkeley.edu>
Reply-To: daveh@cbmvax.cbm.commodore.com (Dave Haynie)
Distribution: usa
Organization: Commodore, West Chester, PA
Lines: 61

In article <1990Feb2.073513.29698@agate.berkeley.edu> laba-3en@web-1c (Raja S Kushalnagar) writes:

>...has almost been able to surmount the difficulties of deep pipelining, though
>it seems not to have surmounted the issue of efficient window register 
>meshing, and probably might not be able to get over it at all, unless it 
>goes more the RISC way, which it already seems to be going towards, but while
>retaining all the advantages of CISCs.  If that can be done, it should really
>perform well. But if it can't really address the issue of utilizing 
>overlapping registers and frames, I wonder if it could improve quickly enough
>to match the RISCs.  

Only a few of the RISCs out are massive register machines with register windows,
etc.  For example, the Motorola 88k only have 32 general purpose registers, and
it's currenly winning the SPECmark wars.  Most RISC chips have at least 32
general registers, but its only the Berleley influenced ones that have register
windows (the two I know of are Sparc and the AMD 29K).  There were independent
RISC projects conducted elsewhere, such as at Stanford, that came up with 
different RISC ideas.  And of course, you can always go back and see what they
did in Supercomputers 5 or 10 years ago -- most early supercomputers were 
necessarily RISCy.

>The same source code when compiled under a DEC 3100 (RISC technology) produced
>binaies that were usually about 30-40% larger than those compiled under a Sun
> 4/260 (CISC technology) 

The Sun 3 series is 68030; all the Sun 4s are Sparcs.  The difference you see
could be the difference between Sparc and the MIPS CPUs DEC uses.  It could also
be operating system stuff -- shared libraries drastically cut the size of
your binaries, other things do as well.

>Interestingly despite the more advanced compilers present with the DEC, it took 
>slightly more time to compile.  

That's exactly what you'd expect, all things being equal.  More optimizations
and other cleverness will always take longer.

>RISC seems to be somewhat superior, given the current technological and 
>economic constraints.  It seems a bit shaky though. 

The thing everyone needs to realize is that there is no one "RISC".  RISC is
more like an architectural bag of tricks designed to make faster CPUs.  Some of 
these tricks can be applied to older CPU designs, others probably can't.  The
one who wins is the one who goes the fastest, regardless of what it took to
get there.  The winner these days changes on a pretty regular basis.  May you
live in interesting times.

>	Raja.

>P.S.  Will the 68040 be pin compatiable with its predecessors?  I thought 
>it ought to be, but some articles have said it wasn't?  

No, the refined the bus arctitecture and various other bits to optimize
the '040's path to external memory in the fastest possible case.  That
just makes it more difficult on designers, (another CPU bus to learn, work
to adapt it to older systems, etc) but as long as you get something in 
return, it's no big deal.

-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
                    Too much of everything is just enough