Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!brutus.cs.uiuc.edu!psuvax1!psuvm!cjc105
From: CJC105@psuvm.psu.edu (Chris)
Newsgroups: comp.sys.amiga.hardware
Subject: Need advice on design project
Message-ID: <90033.211131CJC105@PSUVM.BITNET>
Date: 3 Feb 90 02:11:31 GMT
Organization: Penn State University
Lines: 18

I was thinking about designing an inexpensive processor accelerator for my
final project in a VLSI design class.  Basically, I wanted to model my design
after the CMI accelerator.  What I lack at this time is technical info
(schematic, hardware manual, etc) and I need some quick advice as the proposal
is due 2/9.

From what I understand about the CMI accelerator, it simply doubles the clock
speed of the 68000 while talking to the bus at 7.14Mhz.  The net effect is that
internal operations are done in half the time.   I wanted to improve upon this
design by letting the 68000 talk to the bus at 14.28Mhz when there is no
DMA or Blitter conflit.

If someone could comment about the feasibility of this design, or perhaps
recommend alternate design projects it would be greatly appreciated!


                                               Chris Conrad
                                               CJC105@psuvm (bitnet)